Skip to content
Embedded

Designing Your First Custom PCB: From KiCad Schematic to Gerber Files

30 June 20269 min read0 views
Designing Your First Custom PCB: From KiCad Schematic to Gerber Files
A beginner-friendly walkthrough of the complete PCB design workflow in KiCad — schematic capture, footprint assignment, PCB layout, routing, and generating Gerber files for manufacturing.

Why Custom PCBs Over Breadboards

Breadboard prototypes are essential for rapid iteration, but they are unreliable for deployments. Loose jumper wires fall off, stray inductance corrupts high-frequency signals, and breadboard power rails cannot handle more than ~200mA safely. A custom PCB solves all three problems — it is your hardware, permanently.

The KiCad Workflow

KiCad is a free, open-source EDA (Electronic Design Automation) suite used for professional PCB design. The workflow has five stages:

  1. Schematic Capture (Eeschema)
  2. Footprint Assignment
  3. PCB Layout (PCBnew)
  4. Routing
  5. Gerber Export

Stage 1: Schematic Capture

The schematic is the logical blueprint — it shows component relationships, not physical placement. Wire ESP32 power rails first:

VIN (5V) → AMS1117-3.3 LDO → 3.3V rail
3.3V rail → ESP32 VCC
3.3V rail → 100nF decoupling cap → GND (place cap physically near ESP32 pin)

Decoupling capacitors (100nF) next to every power pin are critical — they suppress high-frequency noise from switching events.

Stage 2: Footprint Assignment

Every schematic symbol needs a physical footprint — the copper pads and silkscreen on the board. For an ESP32-WROOM-32 module, use the RF_Module:ESP32-WROOM-32 footprint from KiCad's library.

Stage 3: PCB Layout Principles

  • Keep analog and digital ground planes separate, joining at a single point.
  • Place decoupling caps within 1-2mm of the power pin they serve.
  • High-current traces (e.g. motor drivers, 500mA+) need wider copper: use the PCB trace width calculator (W = I / (k × ΔT^0.44)).
  • Antenna keepout zones: Keep all copper away from the ESP32 PCB antenna area.

Stage 4: Design Rules Check (DRC)

Before routing, set your manufacturer's DRC constraints (e.g. JLCPCB minimums: 0.2mm trace width, 0.2mm clearance, 0.3mm drill). Run DRC after routing to catch violations.

Stage 5: Gerber Export

Generate: F.Cu, B.Cu, F.Mask, B.Mask, F.Silks, B.Silks, Edge.Cuts, and the drill file (.drl). Zip these and upload to JLCPCB or PCBWay for a 5-unit prototype batch for around $10–$20.

Need a custom PCB designed for your IoT product? Let's talk →

Frequently Asked Questions

Q:What are the minimum trace widths for JLCPCB standard PCB?

JLCPCB standard service supports 0.127mm (5 mil) minimum trace width and 0.127mm minimum clearance for their standard 2-layer boards.

Q:How do I add a ground plane in KiCad PCBnew?

Use Add Filled Zone (Shift+Z), select GND net, draw the boundary around your board, then press B to fill all copper zones. Ground planes reduce EMI and simplify routing.

Working on something similar?

Let's collaborate to design custom PCB schematics, write deterministic FreeRTOS threads, or configure secure Next.js databases.

Let's talk →
FyraAsk anything